Ongoing developments in semiconductor processing technologies and memory cell technologies have continued to increase the density achieved in integrated circuit memory arrays. For example, certain passive element memory cell arrays, such as those including an antifuse cell, may be fabricated having word lines approaching the minimum feature size (F) and minimum feature spacing for the particular word line interconnect layer, and also having bit lines approaching the minimum feature width and minimum feature spacing for the particular bit line interconnect layer. Moreover, three-dimensional memory arrays having more than one plane or level of memory cells have been fabricated implementing such so-called 4F2 memory cells on each memory plane. Exemplary three-dimensional memory arrays are described in U.S. Pat. No. 6,034,882 to Johnson, entitled “Vertically Stacked Field Programrnable Nonvolatile Memory and Method of Fabrication,” and in U.S. Pat. No. 5,835,396 to Zhang, entitled “Three-Dimensional Read-Only Memory Array.”
Implementing such three-dimensional memory arrays having 4F2 memory cells on each memory plane presents challenges in the design and layout of decoding and memory layer interface circuitry capable of interfacing with such tightly-pitched array lines.